Technical Field
The present invention relates to an inductor element formed on a semiconductor substrate, a method for manufacturing the same, and a semiconductor device including the inductor element.
Background Art
With the miniaturization and high integration of recent semiconductor elements, induction elements formed of metal leads, i.e., inductor elements, are formed in semiconductor devices with the goal of improving operation frequencies and achieving low noise/high stability.
Transistors, which are components of semiconductor devices, are undergoing performance improvement by miniaturization, high integration, and the like. However, the inductance of an inductor element is determined by a current flowing in a metal lead and a magnetic field created by the current; and therefore, when a circuit designer attempts to realize a desired inductance value, a chip surface area is necessary of at least several tens of μm by several tens of μm, and when large, several hundreds of μm by several hundreds of μm; and this results in an increase of the chip surface area and likewise causes an increase of the manufacturing cost of the semiconductor device. In other words, even in the case where a miniaturization is performed for structural elements of a semiconductor device including transistors and the like, the scaling, i.e., miniaturization, of an inductor element is difficult in principle; and therefore, the inductor element unfortunately results in a cost increase of the semiconductor device.
Further, in the case where a silicon substrate is used as a substrate that forms the semiconductor device, the performance of the inductor element deteriorates due to losses originating in the silicon substrate at the lower portion of the inductor element due to a high conductivity and a high relative dielectric constant of the silicon substrate. This mainly appears as a lower self-resonant frequency due to a parasitic capacitance between the metal lead forming the inductor element and the silicon substrate.
Also, for a semiconductor device using metal leads made of copper and having copper as a main component that are formed by a recently mainstream damascene process, a flattening process is performed for retaining the planarity of the inter-layer insulative film; and therefore, it is necessary to lay island shaped metal (hereinbelow, referred to as “dummy metal”) also in the regions where metal leads are not formed; but the dummy metal exists between inductor leads and the silicon substrate; and thereby, the practically effective distance between the inductor leads and the silicon substrate is reduced by the amount of the thickness of the dummy metal; and as a result, the parasitic capacitance unfortunately increases.
To solve these problems, for example, technology disclosed in Patent Literature 1, Patent Literature 2, and Patent Literature 3 forms inductor elements by forming a spiral inductor in each layer of laminated multiple lead layers and connecting the spiral inductor of each lead layer in series, and thereby improves the inductance per unit surface area. FIG. 22 is a schematic perspective view of an essential portion of a semiconductor device disclosed in Patent Literature 1; FIG. 23A is a schematic top view illustrating a spiral inductor of a layer below a semiconductor device disclosed in Patent Literature 2; FIG. 23B is a schematic top view illustrating a spiral inductor of an upper layer of the same; and FIG. 24 is a schematic top view illustrating a spiral inductor of a semiconductor integrated circuit disclosed in Patent Literature 3.
As illustrated in FIG. 22 to FIG. 24, in the case where an inductor element is formed by making a spiral inductor using two lead layers and connecting these in series, about twice the inductance value can be obtained in comparison to an inductor element formed using a single lead layer having the same surface area.
Also, in Patent Literature 4 and Patent Literature 5, a solenoid shaped inductor element, which is formed by laminating annular leads that have a notch in a portion and mutually connecting these in series, is disclosed.
FIG. 25A is a schematic top view from a second lead 52 side of a semiconductor device disclosed in Patent Literature 6; and FIG. 25B is a schematic bottom view from a first lead 51 side (semiconductor substrate side) of the same. Technology disclosed in Patent Literature 6 reduces a signal delay between the upper and lower leads of the inductor element formed by two layers of metal leads, i.e., the first lead 51 and the second lead 52, and inhibits a decrease of the inductance value due to a negative mutual inductance.
Patent Literature 1: Unexamined Japanese Utility Model Application Publication No. S60-136156
Patent Literature 2: Unexamined Japanese Patent Application KOKAI Publication No. S61-265857
Patent Literature 3: Unexamined Japanese Patent Application KOKAI Publication No. H03-089548
Patent Literature 4: Unexamined Japanese Patent Application KOKAI Publication No. 2001-351980
Patent Literature 5: Unexamined Japanese Patent Application KOKAI Publication No. H06-61058
Patent Literature 6: U.S. Pat. No. 2,976,926